CMOS semiconductor transistors, both P-type and N-type, are identified with two parameters, namely their threshold voltage—the voltage needed between the gate of a transistor and its source to turn it on—and their saturation current as a reflection of their drive strength. These two transistor parameters, the threshold voltage and the saturation current, are reflected in the speed of circuits in which such transistors are used as basic components.
CMOS transistors, P-type and N-type undergo a change—degradation—in their threshold voltage and saturation current over time. This degradation in the threshold voltage and saturation current of a transistor takes the form of an increase in the magnitude of the threshold voltage and a decrease in the magnitude of the saturation current. There are several physics based phenomena that cause such degradation.
One phenomenon is elevated electric fields between the gate of the transistor and its drain, known as hot carrier injection (HCI) resulting in a permanent shift in threshold voltage. Another phenomenon is “biased thermal instability” (BTI) that causes partially recoverable degradation in the threshold voltage of the transistor. BTI is highly dependent on temperature, total switching time, and the switching behavior of the transistor also known as the switching duty cycle. The BTI-induced change in the threshold voltage and saturation current of P-transistors is referred to as “negative bias thermal instability” (NBTI).
The NBTI phenomenon is a partially reversible process. When the applied source-to-gate bias is removed, the transistor is capable of recovering part of the change in threshold voltage and in saturation current brought about by the applied bias. The amount of recovery is heavily dependent on the duration of the absence of any source-to-gate bias. However, a partial recovery is usually fast.
Modeling NBTI is important for accurate circuit simulation. Because of the partial recovery aspect of NBTI, accurate modeling is heavily dependent on minimizing the amount of time between the application of the source-to-gate bias and the measurement of the magnitude of change in the threshold voltage and saturation current.
FIG. 1 illustrates a standard NBTI test setup representing the current state of the art. A bench tester 10 applies an external voltage bias of zero volts to the gate of the transistor P10 and measures the current flowing through the transistor. Then the P-transistor P10 is stressed through applying a stress voltage Vg at the gate of the transistor P10 and through applying a voltage Vdd, equal to the source voltage of P10, the drain of the transistor P10 to keep the potential between the source and the drain of P10 at zero during the stress phase of the test as shown in waveform 20. After the stress period is complete, the tester 10 releases the applied voltages to the gate and drain of transistor P10 and re-applies a bias of zero volts to the gate of the transistor P10. The tester then measures the new value of the current flowing through the transistor. There is usually a delay between the stress phase and the measurement phase determined by the tester limitations and specifications. During this delay, the transistor partially recovers from the NBTI effects. Thus the measured NBTI effect is lower than the actual NBTI effect.